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CGO
2005
IEEE
15 years 11 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
ISCA
2003
IEEE
150views Hardware» more  ISCA 2003»
15 years 10 months ago
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
Dan Ernst, Andrew Hamel, Todd M. Austin
ASPDAC
2005
ACM
93views Hardware» more  ASPDAC 2005»
15 years 7 months ago
Power minimization for dynamic PLAs
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, ...
SENSYS
2010
ACM
15 years 3 months ago
Enix: a lightweight dynamic operating system for tightly constrained wireless sensor platforms
Enix is a lightweight dynamic operating system for tightly constrained platforms for wireless sensor networks (WSN). Enix provides a cooperative threading model, which is applicab...
Yu-Ting Chen, Ting-Chou Chien, Pai H. Chou
VLDB
2007
ACM
119views Database» more  VLDB 2007»
16 years 5 months ago
Dynamic Workload Management for Very Large Data Warehouses: Juggling Feathers and Bowling Balls
Workload management for business intelligence (BI) queries poses different challenges than those addressed in the online transaction processing (OLTP) context. The fundamental pro...
Stefan Krompass, Umeshwar Dayal, Harumi A. Kuno, A...