339 search results - page 14 / 68 » An ADC-BiST scheme using sequential code analysis |
PPOPP
2012
ACM
13 years 7 months ago
2012
ACM
We present Dynamic Out-of-Order Java (DOJ), a dynamic parallelization approach. In DOJ, a developer annotates code blocks as tasks to decouple these blocks from the parent executi...
IPPS
2006
IEEE
15 years 5 months ago
2006
IEEE
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
101
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ISSTA
2010
ACM
15 years 1 months ago
2010
ACM
SAT-based bounded verification of annotated code consists of translating the code together with the annotations to a propositional formula, and analyzing the formula for specifica...
104
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DAC
2000
ACM
16 years 19 days ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
ENTCS
2007
14 years 11 months ago
2007
A major development in qualitative model checking was the jump to verifying properties of source code directly, rather than requiring a separately specified model. We describe an...