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» An ASIP design methodology for embedded systems
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DATE
2006
IEEE
82views Hardware» more  DATE 2006»
15 years 7 months ago
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Although, leakage power is becoming increasingly more important as technology feature...
Po-Kuan Huang, Soheil Ghiasi
RSP
1998
IEEE
110views Control Systems» more  RSP 1998»
15 years 5 months ago
Rapid Design of Discrete Orthonormal Wavelet Transforms
A rapid design methodology for orthonormal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture utilising time-interleaved co...
Shahid Masud, John V. McCanny
DATE
2006
IEEE
105views Hardware» more  DATE 2006»
15 years 7 months ago
Comfortable modeling of complex reactive systems
Modeling systems based on semi-formal graphical formalisms, such as Statecharts, has become standard practice in the design of reactive embedded devices. However, the modeling of ...
Steffen Prochnow, Reinhard von Hanxleden
JCP
2008
216views more  JCP 2008»
15 years 1 months ago
Design Overview Of Processor Based Implantable Pacemaker
Implantable pacemaker is a battery operated real time embedded system, which includes software/hardware codesign strategy. As it is placed within the heart by surgery, battery life...
Santosh D. Chede, Kishore D. Kulat
SAMOS
2005
Springer
15 years 7 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...