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» An Access Timing Measurement Unit of Embedded Memory
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HPCA
2001
IEEE
16 years 5 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
LCTRTS
2010
Springer
16 years 3 days ago
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture
A large number of embedded systems include 8-bit microcontrollers for their energy efficiency and low cost. Multi-bank memory architecture is commonly applied in 8-bit microcontr...
Minming Li, Chun Jason Xue, Tiantian Liu, Yingchao...
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
15 years 11 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...
RTAS
2000
IEEE
15 years 9 months ago
Chocolate: A Reservation-Based Real-Time Java Environment on Windows/NT
In this paper, we present Chocolate, a reservation-based Real-Time Java run-time environment that runs on Windows NT. We first present a brief overview of the emerging RealTime Ja...
Dionisio de Niz, Ragunathan Rajkumar
208
Voted
IESS
2009
Springer
182views Hardware» more  IESS 2009»
15 years 3 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer