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» An Advanced Optimizer for the IA-64 Architecture
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ICCD
2004
IEEE
125views Hardware» more  ICCD 2004»
15 years 6 months ago
IPC Driven Dynamic Associative Cache Architecture for Low Energy
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
Sriram Nadathur, Akhilesh Tyagi
IISWC
2006
IEEE
15 years 3 months ago
An Architectural Characterization Study of Data Mining and Bioinformatics Workloads
— Data mining is the process of automatically finding implicit, previously unknown, and potentially useful information from large volumes of data. Recent advances in data extrac...
Berkin Özisikyilmaz, Ramanathan Narayanan, Jo...
CORR
2011
Springer
139views Education» more  CORR 2011»
14 years 1 months ago
Volatility of Power Grids under Real-Time Pricing
—The paper proposes a framework for modeling and analysis of the dynamics of supply, demand, and clearing prices in power system with real-time retail pricing and information asy...
Mardavij Roozbehani, Munther Dahleh, Sanjoy K. Mit...
ISSA
2004
14 years 11 months ago
High Data Rate 8-Bit Crypto Processor
This paper describes a high data rate 8-bit Crypto Processor based on Advanced Encryption Standard (Rijndael algorithm). Though the algorithm requires 32-bit wide data path but ou...
Sheikh Muhammad Farhan
76
Voted
ASPLOS
1989
ACM
15 years 1 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....