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» An Advanced Optimizer for the IA-64 Architecture
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DSD
2006
IEEE
183views Hardware» more  DSD 2006»
15 years 4 months ago
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption h...
Panu Hämäläinen, Timo Alho, Marko H...
IPPS
1999
IEEE
15 years 2 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
ARC
2009
Springer
165views Hardware» more  ARC 2009»
15 years 4 months ago
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
Abstract. Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integr...
Xu Guo, Patrick Schaumont
DLOG
2001
14 years 11 months ago
Combining Tableaux and Algebraic Methods for Reasoning with Qualified Number Restrictions
This paper investigates an optimization technique for reasoning with qualified number restrictions in the description logic ALCQHR+ . We present a hybrid architecture where a stan...
Volker Haarslev, Martina Timmann, Ralf Möller
DAC
2003
ACM
15 years 3 months ago
Performance trade-off analysis of analog circuits by normal-boundary intersection
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
Guido Stehr, Helmut E. Graeb, Kurt Antreich