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» An Algorithm for Bi-Decomposition of Logic Functions
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PEPM
2007
ACM
15 years 3 months ago
Poly-controlled partial evaluation in practice
Poly-Controlled Partial Evaluation (PCPE) is a powerful approach to partial evaluation, which has recently been proposed. PCPE takes into account sets of control strategies instea...
Claudio Ochoa, Germán Puebla
CODES
2005
IEEE
15 years 3 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 3 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
TABLEAUX
2005
Springer
15 years 3 months ago
A Tableau-Based Explainer for DL Subsumption
This paper describes the implementation of a tableau-based reasoning component which is capable of providing quasi natural language explanations for subsumptions within ALEHFR+ TBo...
Thorsten Liebig, Michael Halfmann
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Node Mergers in the Presence of Don't Cares
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Vale...