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ISVLSI
2007
IEEE
151views VLSI» more  ISVLSI 2007»
15 years 4 months ago
Design of a MCML Gate Library Applying Multiobjective Optimization
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
Roberto Pereira-Arroyo, Pablo Alvarado-Moya, Wolfg...
ICAIL
2007
ACM
15 years 1 months ago
The Ontology of Legal Possibilities and Legal Potentialities
Ontologies in a legal expert system must be processed to suit all possible user cases within the field of law of the system. From the logical premises of a deductive system of expr...
Pamela N. Gray
IPPS
2006
IEEE
15 years 3 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
15 years 3 months ago
Technology Mapping for Reliability Enhancement in Logic Synthesis
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
Zhaojun Wo, Israel Koren
VLSID
2006
IEEE
156views VLSI» more  VLSID 2006»
15 years 10 months ago
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to deve...
Jungsub Kim, Mary Jane Irwin, Narayanan Vijaykrish...