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» An Analytical Model of Multistage Interconnection Networks
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MASCOTS
2004
13 years 7 months ago
Performance Modeling of Fully Adaptive Wormhole Routing in 2-D Mesh-Connected Multiprocessors
Several models of deterministic routing have been proposed for wormhole-routed mesh networks while there is only one model, to our best knowledge, proposed for fully adaptive worm...
Hashem Hashemi Najaf-abadi, Hamid Sarbazi-Azad, P....
NOCS
2007
IEEE
14 years 15 days ago
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
Abstract – With the rise of multicore computing, the design of onchip networks (or networks on chip) has become an increasingly important component of computer architecture. The ...
Thomas William Ainsworth, Timothy Mark Pinkston
SLIP
2005
ACM
13 years 11 months ago
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
Young-Su Kwon, Payam Lajevardi, Anantha P. Chandra...
SAINT
2005
IEEE
13 years 11 months ago
On Scalable Modeling of TCP Congestion Control Mechanism for Large-Scale IP Networks
In this paper, we propose an analytic approach of modeling a closed-loop network with multiple feedback loops using fluid-flow approximation. Specifically, we model building bl...
Hiroyuki Ohsaki, Juñya Ujiie, Makoto Imase
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
14 years 3 months ago
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Io...