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ETS
2006
IEEE
89views Hardware» more  ETS 2006»
15 years 1 months ago
On-Chip Time Measurement Architecture with Femtosecond Timing Resolution
This paper presents a new on-chip time measurement architecture which is based on the Timeto-Digital Conversion (TDC) method that is capable of achieving a timing resolution of te...
Matthew Collins, Bashir M. Al-Hashimi
ICCD
1992
IEEE
83views Hardware» more  ICCD 1992»
15 years 1 months ago
Logical Verification of the NVAX CPU Chip Design
ct Digital's NVAX high-performance microprocessor has a complex logical design. A rigorous simulation-based verification effort was undertaken to ensure that there were no log...
Walker Anderson
DAC
2004
ACM
15 years 3 months ago
A timing-driven module-based chip design flow
A Module-Rased design flow for digital ICs with hard and sofl modules is presented. Versions of the sofl modules are implemented with different areddelay characteristics. The vers...
Fan Mo, Robert K. Brayton
DAC
1999
ACM
15 years 2 months ago
Robust Techniques for Watermarking Sequential Circuit Designs
We present a methodology for the watermarking of synchronous sequential circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on th...
Arlindo L. Oliveira
UIST
2003
ACM
15 years 3 months ago
Fluid interaction techniques for the control and annotation of digital video
We explore a variety of interaction and visualization techniques for fluid navigation, segmentation, linking, and annotation of digital videos. These techniques are developed with...
Gonzalo Ramos, Ravin Balakrishnan