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» An Architecture for Adaptive Algorithmic Hybrids
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DAC
2006
ACM
16 years 1 months ago
A new LP based incremental timing driven placement for high performance designs
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
Tao Luo, David Newmark, David Z. Pan
98
Voted
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
15 years 6 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
BERTINORO
2005
Springer
15 years 6 months ago
On the Use of Online Analytic Performance Models, in Self-Managing and Self-Organizing Computer Systems
Current computing environments are becoming increasingly complex in nature and exhibit unpredictable workloads. These environments create challenges to the design of systems that c...
Daniel A. Menascé, Mohamed N. Bennani, Hong...
117
Voted
AAECC
2007
Springer
87views Algorithms» more  AAECC 2007»
15 years 19 days ago
Towards an accurate performance modeling of parallel sparse factorization
We present a simulation-based performance model to analyze a parallel sparse LU factorization algorithm on modern cached-based, high-end parallel architectures. We consider supern...
Laura Grigori, Xiaoye S. Li
112
Voted
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
15 years 2 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy