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FPGA
2006
ACM
111views FPGA» more  FPGA 2006»
15 years 3 months ago
FPGA clock network architecture: flexibility vs. area and power
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
Julien Lamoureux, Steven J. E. Wilton
PRICAI
2000
Springer
15 years 3 months ago
Virtual Enterprise Design - BDI Agents vs. Objects
Current research identifying architectures for a virtual enterprise has moved from information modelling to role modelling. Thus, a high level of autonomy results from the distribu...
Iyad Rahwan, Ryszard Kowalczyk, Yun Yang
CORR
2008
Springer
107views Education» more  CORR 2008»
14 years 11 months ago
A Computational Framework for the Near Elimination of Spreadsheet Risk
We present Risk Integrated's Enterprise Spreadsheet Platform (ESP), a technical approach to the near-elimination of spreadsheet risk in the enterprise computing environment, ...
Yusuf Jafry, Fredrika Sidoroff, Roger Chi
ASPDAC
1995
ACM
77views Hardware» more  ASPDAC 1995»
15 years 3 months ago
A scheduling algorithm for synthesis of bus-partitioned architectures
- Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach ...
Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi T...
FPGA
2008
ACM
168views FPGA» more  FPGA 2008»
15 years 24 days ago
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs
The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an ...
Alessandro Cevrero, Panagiotis Athanasopoulos, Had...