33 search results - page 6 / 7 » An Architecture for Fault-Tolerant Computation with Stochast... |
DAC
2001
ACM
14 years 7 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
DAC
2009
ACM
14 years 7 months ago
2009
ACM
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
DAC
2007
ACM
14 years 7 months ago
2007
ACM
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
ATAL
2008
Springer
13 years 8 months ago
2008
Springer
In this paper, we describe two mission critical applications currently deployed by Telecom Italia in the Operations Support System domains. The first one called "Network Neut...