1269 search results - page 218 / 254 » An Architecture for Parallel Topic Models |
113
click to vote
HPCA
2011
IEEE
14 years 3 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
107
click to vote
PPOPP
2009
ACM
16 years 10 days ago
2009
ACM
Due to power wall, memory wall, and ILP wall, we are facing the end of ever increasing single-threaded performance. For this reason, multicore and manycore processors are arising ...
101
click to vote
HCW
1998
IEEE
15 years 4 months ago
1998
IEEE
A distributed, parallel implementation of the widely used Modular Semi-Automated Forces ModSAF Distributed Interactive Simulation DIS is presented, with Scalable Parallel Processo...
VLSID
2007
IEEE
16 years 5 days ago
2007
IEEE
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
IEEEPACT
2009
IEEE
15 years 6 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...