2 search results - page 1 / 1 » An Area-Efficient FPGA-Based Architecture for Fully-Parallel... |
98
Voted
SIPS
2007
IEEE
15 years 7 months ago
2007
IEEE
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
92
Voted
TSP
2008
15 years 28 days ago
2008
Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) dec...