29 search results - page 3 / 6 » An Axiomatic Memory Model for POWER Multiprocessors |
110
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IEEEPACT
2006
IEEE
15 years 5 months ago
2006
IEEE
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
82
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ISCA
1997
IEEE
15 years 3 months ago
1997
IEEE
The SGI Origin 2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor designed and manufactured by Silicon Graphics, Inc. The Origin system was designed from t...
73
Voted
ISCA
1998
IEEE
15 years 3 months ago
1998
IEEE
A memory model for a shared memory, multiprocessor commonly and often implicitly assumed by programmers is that of sequential consistency. This model guarantees that all memory ac...
109
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IEEEHPCS
2010
14 years 9 months ago
2010
Stream languages explicitly describe fork-join parallelism and pipelines, offering a powerful programming model for many-core Multi-Processor Systems on Chip (MPSoC). In an embedd...