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» An Axiomatic Memory Model for POWER Multiprocessors
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81
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ISPASS
2009
IEEE
15 years 4 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
ICPIA
1992
15 years 1 months ago
Parallel Manipulations of Octrees and Quadtrees
Abstract. Octrees o er a powerful means for representing and manipulating 3-D objects. This paper presents an implementation of octree manipulations using a new approach on a share...
Vipin Chaudhary, K. Kamath, Prakash Arunachalam, J...
ICDE
2006
IEEE
206views Database» more  ICDE 2006»
15 years 11 months ago
Query Co-Processing on Commodity Hardware
The rapid increase in the data volumes for the past few decades has intensified the need for high processing power for database and data mining applications. Researchers have acti...
Anastassia Ailamaki, Naga K. Govindaraju, Dinesh M...
RTAS
2010
IEEE
14 years 7 months ago
Timing Analysis for TDMA Arbitration in Resource Sharing Systems
Abstract--Modern computing systems have adopted multicore architectures and multiprocessor systems on chip (MPSoCs) for accommodating the increasing demand on computation power. Ho...
Andreas Schranzhofer, Jian-Jia Chen, Lothar Thiele
84
Voted
SPIN
2007
Springer
15 years 3 months ago
Tutorial: Parallel Model Checking
d Abstract) Luboˇs Brim and Jiˇr´ı Barnat Faculty of Informatics, Masaryk University, Brno, Czech Republic With the increase in the complexity of computer systems, it becomes e...
Lubos Brim, Jiri Barnat