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92
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ICES
2001
Springer
140views Hardware» more  ICES 2001»
15 years 2 months ago
A VLSI Implementation of an Analog Neural Network Suited for Genetic Algorithms
The usefulness of an artificial analog neural network is closely bound to its trainability. This paper introduces a new analog neural network architecture using weights determined...
Johannes Schemmel, Karlheinz Meier, Felix Schü...
78
Voted
ERSA
2006
91views Hardware» more  ERSA 2006»
14 years 11 months ago
Intrinsic Embedded Hardware Evolution of Block-based Neural Networks
- An intrinsic embedded online evolution system has been designed using Block-based neural networks and implemented on Xilinx VirtexIIPro FPGAs. The designed network can dynamicall...
Saumil Merchant, Gregory D. Peterson, Seong Kong
73
Voted
ISCAS
2007
IEEE
106views Hardware» more  ISCAS 2007»
15 years 4 months ago
Area-Power Efficient Lifting-Based DWT Hardware for Implantable Neuroprosthetics
— Discrete wavelet transform (DWT) has been shown to provide exceptionally efficient data compression for neural records. This paper describes an area-power minimized hardware im...
Awais M. Kamboh, Matthew Raetz, Andrew Mason, Kari...
83
Voted
PREMI
2005
Springer
15 years 3 months ago
Artificial Neural Network Engine: Parallel and Parameterized Architecture Implemented in FPGA
In this paper we present and analyze an artificial neural network hardware engine, its architecture and implementation. The engine was designed to solve performance problems of the...
Milene Barbosa Carvalho, Alexandre Marques Amaral,...
111
Voted
ANNPR
2006
Springer
15 years 7 days ago
A Convolutional Neural Network Tolerant of Synaptic Faults for Low-Power Analog Hardware
Abstract. Recently, the authors described a training method for a convolutional neural network of threshold neurons. Hidden layers are trained by by clustering, in a feed-forward m...
Johannes Fieres, Karlheinz Meier, Johannes Schemme...