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CAL
2007
13 years 7 months ago
Logic-Based Distributed Routing for NoCs
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...
José Flich, José Duato
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 1 months ago
A highly resilient routing algorithm for fault-tolerant NoCs
Current trends in technology scaling foreshadow worsening transistor reliability as well as greater numbers of transistors in each system. The combination of these factors will so...
David Fick, Andrew DeOrio, Gregory K. Chen, Valeri...
DATE
2007
IEEE
107views Hardware» more  DATE 2007»
14 years 1 months ago
Routing table minimization for irregular mesh NoCs
The majority of current Network on Chip (NoC) architectures employ mesh topology and use simple static routing, to reduce power and area. However, regular mesh topology is unreali...
Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam...
SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
14 years 20 days ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...