Sciweavers

40 search results - page 3 / 8
» An Efficient Model for DSP Code Generation: Performance, Cod...
Sort
View
CODES
2001
IEEE
13 years 10 months ago
Evaluating register file size in ASIP design
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A ke...
Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, P...
ICIP
2006
IEEE
14 years 8 months ago
On the Modeling of Motion in Wyner-Ziv Video Coding
In the past few years, a number of practical video coding schemes following distributed source coding principles have emerged. One of the main goals of distributed video coding (D...
Marco Tagliasacchi, Stefano Tubaro, Augusto Sarti
EMSOFT
2004
Springer
13 years 11 months ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande
WSC
1997
13 years 7 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
NIPS
2001
13 years 7 months ago
Correlation Codes in Neuronal Populations
Population codes often rely on the tuning of the mean responses to the stimulus parameters. However, this information can be greatly suppressed by long range correlations. Here we...
Maoz Shamir, Haim Sompolinsky