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» An Efficient Path Delay Fault Coverage Estimator
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ICCAD
2005
IEEE
97views Hardware» more  ICCAD 2005»
15 years 6 months ago
DiCER: distributed and cost-effective redundancy for variation tolerance
— Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance techn...
Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, ...
DATE
2004
IEEE
120views Hardware» more  DATE 2004»
15 years 1 months ago
Pattern Selection for Testing of Deep Sub-Micron Timing Defects
Due to process variations in deep sub-micron (DSM) technologies, the effects of timing defects are difficult to capture. This paper presents a novel coverage metric for estimating...
Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng
TON
2008
126views more  TON 2008»
14 years 9 months ago
Hyperbolic embedding of internet graph for distance estimation and overlay construction
Estimating distances in the Internet has been studied in the recent years due to its ability to improve the performance of many applications, e.g., in the peer-topeer realm. One sc...
Yuval Shavitt, Tomer Tankel
ISLPED
2007
ACM
92views Hardware» more  ISLPED 2007»
14 years 11 months ago
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh
ISCAS
2007
IEEE
180views Hardware» more  ISCAS 2007»
15 years 3 months ago
Characterization of a Fault-tolerant NoC Router
— With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip (SoC) and multicore ...
Sumit D. Mediratta, Jeffrey T. Draper