60 search results - page 5 / 12 » An Efficient Path Delay Fault Coverage Estimator |
64
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
VTS
1997
IEEE
15 years 1 months ago
1997
IEEE
Despite all of the advantages that circular BIST ofsers compared to conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion, it has se...
103
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ITC
1993
IEEE
15 years 1 months ago
1993
IEEE
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
87
Voted
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
IOLTS
2005
IEEE
15 years 3 months ago
2005
IEEE
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...