60 search results - page 6 / 12 » An Efficient Path Delay Fault Coverage Estimator |
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
－ We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and cr...
75
Voted
IPPS
2002
IEEE
15 years 2 months ago
2002
IEEE
This paper proposes a new distributed shortest path (SP) based delay constrained multicast routing algorithm which is capable of constructing a delay constrained multicast tree wh...
DATE
1998
IEEE
15 years 1 months ago
1998
IEEE
Most memory test algorithms are optimized tests for a particular memory technology and a particular set of fault models, under the assumption that the memory is bit-oriented; i.e....
CORR
2010
Springer
14 years 9 months ago
2010
Springer
In sensor networks communication by broadcast methods involves many hazards, especially collision. Several MAC layer protocols have been proposed to resolve the problem of collisi...
TVLSI
2002
14 years 9 months ago
2002
Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simp...