48 search results - page 3 / 10 » An Embedded IDDQ Testing Architecture and Technique |
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
Reduction of both the test suite size and the download time of test vectors is important in today's System-On-a-Chip designs. In this paper, a method for compressing the scan...
DAC
1997
ACM
13 years 10 months ago
1997
ACM
Novel test bench techniques are required to cope with a functional test complexity which is predicted to grow much more strongly than design complexity. Our test bench approach at...
ETS
2006
IEEE
14 years 14 days ago
2006
IEEE
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these netwo...
DAC
2012
ACM
11 years 8 months ago
2012
ACM
Many state-of-the-art approaches on fault-tolerant system design make the simplifying assumption that all faults are detected within a certain time interval. However, based on a d...
GECCO
2004
Springer
13 years 11 months ago
2004
Springer
Abstract. The need for effective testing techniques for architectural level descriptions is widely recognised. However, due to the variety of domain-specific architectural descript...