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ASPDAC
2007
ACM
100views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
DAC
2009
ACM
15 years 1 months ago
RegPlace: a high quality open-source placement framework for structured ASICs
Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low ...
Ashutosh Chakraborty, Anurag Kumar, David Z. Pan
CSE
2009
IEEE
15 years 24 days ago
Rotation Scheduling and Voltage Assignment to Minimize Energy for SoC
— Low energy consumption is a critical issue in embedded systems design. As the technology feature sizes of SoC (Systems on Chip) become smaller and smaller, the percentage of le...
Meikang Qiu, Laurence Tianruo Yang, Edwin Hsing-Me...
AAAI
2007
14 years 12 months ago
Counting CSP Solutions Using Generalized XOR Constraints
We present a general framework for determining the number of solutions of constraint satisfaction problems (CSPs) with a high precision. Our first strategy uses additional binary...
Carla P. Gomes, Willem Jan van Hoeve, Ashish Sabha...
DAC
2005
ACM
14 years 11 months ago
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty