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97
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DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
15 years 7 months ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
ISCAS
2006
IEEE
145views Hardware» more  ISCAS 2006»
15 years 6 months ago
The wordlength determination problem of linear time invariant systems with multiple outputs - a geometric programming approach
This paper proposes two new methods for optimizing objectives and constraints. The GP approach is very general and hardware resources in finite wordlength implementation of it allo...
S. C. Chan, K. M. Tsui
114
Voted
RTAS
2005
IEEE
15 years 6 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
109
Voted
ISRR
2005
Springer
118views Robotics» more  ISRR 2005»
15 years 6 months ago
A Provably Consistent Method for Imposing Sparsity in Feature-Based SLAM Information Filters
An open problem in Simultaneous Localization and Mapping (SLAM) is the development of algorithms which scale with the size of the environment. A few promising methods exploit the ...
Matthew Walter, Ryan Eustice, John J. Leonard
CRYPTO
2004
Springer
120views Cryptology» more  CRYPTO 2004»
15 years 6 months ago
Round-Optimal Secure Two-Party Computation
Abstract. We consider the central cryptographic task of secure twoparty computation, where two parties wish to compute some function of their private inputs (each receiving possibl...
Jonathan Katz, Rafail Ostrovsky