644 search results - page 26 / 129 » An Experimental Chip to Evaluate Test Techniques: Experiment... |
118
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TVLSI
2008
14 years 11 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
MICRO
2007
IEEE
15 years 6 months ago
2007
IEEE
As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future ...
ASPDAC
2007
ACM
15 years 3 months ago
2007
ACM
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface d...
ICPR
2000
IEEE
16 years 27 days ago
2000
IEEE
This paper compares two techniques for measuring the length of a digital curve. Both techniques (digital straight segment approximation, minimum length polygon) are known to be co...
121
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EUROPAR
2010
Springer
15 years 20 hour ago
2010
Springer
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...