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BMCBI
2005
145views more  BMCBI 2005»
14 years 11 months ago
CAGER: classification analysis of gene expression regulation using multiple information sources
Background: Many classification approaches have been applied to analyzing transcriptional regulation of gene expressions. These methods build models that can explain a gene's...
Jianhua Ruan, Weixiong Zhang
CSE
2009
IEEE
15 years 3 months ago
Rotation Scheduling and Voltage Assignment to Minimize Energy for SoC
— Low energy consumption is a critical issue in embedded systems design. As the technology feature sizes of SoC (Systems on Chip) become smaller and smaller, the percentage of le...
Meikang Qiu, Laurence Tianruo Yang, Edwin Hsing-Me...
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
15 years 6 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
ISCA
2000
IEEE
90views Hardware» more  ISCA 2000»
15 years 4 months ago
A scalable approach to thread-level speculation
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
ASPDAC
2006
ACM
91views Hardware» more  ASPDAC 2006»
15 years 5 months ago
Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs
— In this paper, we introduce a novel substrate noise estimation technique during early floorplanning, based on the concept of Block Preference Directed Graph (BPDG) and the cla...
Minsik Cho, Hongjoong Shin, David Z. Pan