Sciweavers

19 search results - page 3 / 4
» An FPGA Network Architecture for Accelerating 3DES - CBC
Sort
View
FPL
2009
Springer
156views Hardware» more  FPL 2009»
13 years 11 months ago
A highly scalable Restricted Boltzmann Machine FPGA implementation
Restricted Boltzmann Machines (RBMs) — the building block for newly popular Deep Belief Networks (DBNs) — are a promising new tool for machine learning practitioners. However,...
Sang Kyun Kim, Lawrence C. McAfee, Peter L. McMaho...
ICC
2007
IEEE
137views Communications» more  ICC 2007»
14 years 18 days ago
A Novel Algorithm and Architecture for High Speed Pattern Matching in Resource-Limited Silicon Solution
— Network Intrusion Detection Systems (NIDS) are more and more important for identifying and preventing the malicious attacks over the network. This paper proposes a novel cost-e...
Nen-Fu Huang, Yen-Ming Chu, Chi-Hung Tsai, Chen-Yi...

Lecture Notes
1005views
15 years 6 months ago
Lectures on reconfigurable computing
Driven by recent innovations in Field-Programmable Gate Arrays (FPGAs), reconfigurable computing offers unique ways to accelerate key algorithms. FPGAs offer a programmable logic f...
Sherief Reda
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
14 years 9 days ago
A Scalable FPGA-based Multiprocessor
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
Arun Patel, Christopher A. Madill, Manuel Salda&nt...
DDECS
2009
IEEE
116views Hardware» more  DDECS 2009»
13 years 7 months ago
MTPP - Modular Traffic Processing Platform
High-speed (10 Gb/s and above) network monitoring and traffic processing requires hardware acceleration. Different applications require different functions to be placed in hardware...
Jiri Halak, Sven Ubik