17 search results - page 3 / 4 » An FPGA architecture for CABAC decoding in manycore systems |
RSP
2008
IEEE
14 years 18 days ago
2008
IEEE
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
DATE
2005
IEEE
13 years 12 months ago
2005
IEEE
This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent st...
DSD
2008
IEEE
14 years 20 days ago
2008
IEEE
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of commun...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for...
FPL
2007
Springer
14 years 11 days ago
2007
Springer
Multiprocessor systems-on-chip (MPSoC) are being developed in increasing numbers to support the high number of applications running on modern embedded systems. Designing and progr...