27 search results - page 4 / 6 » An Improved Algorithm for Minimum-Area Retiming |
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...
124
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ICPP
1996
IEEE
15 years 1 months ago
1996
IEEE
Data locality and synchronization overhead are two important factors that affect the performance of applications on multiprocessors. Loop fusion is an effective way for reducing s...
ICCAD
1998
IEEE
15 years 1 months ago
1998
IEEE
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...
67
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DAC
2008
ACM
15 years 10 months ago
2008
ACM
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
177
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DAC
2011
ACM
13 years 9 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...