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» An Input Output HMM Architecture
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ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 4 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
IESS
2007
Springer
156views Hardware» more  IESS 2007»
15 years 5 months ago
Automatic Data Path Generation from C code for Custom Processors
The stringent performance constraints and short time to market of modern digital systems require automatic methods for design of high performance applicationspecific architectures...
Jelena Trajkovic, Daniel Gajski
DAC
2003
ACM
15 years 5 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
15 years 3 months ago
Rate analysis for streaming applications with on-chip buffer constraints
While mapping a streaming (such as multimedia or network packet processing) application onto a specified architecture, an important issue is to determine the input stream rates tha...
Alexander Maxiaguine, Simon Künzli, Samarjit ...
IJCNN
2008
IEEE
15 years 6 months ago
Learning associations of conjuncted fuzzy sets for data prediction
— Fuzzy Associative Conjuncted Maps (FASCOM) is a fuzzy neural network that represents information by conjuncting fuzzy sets and associates them through a combination of unsuperv...
Hanlin Goh, Joo-Hwee Lim, Chai Quek