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» An Integer Linear Programming Approach to Database Design
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DATE
2009
IEEE
133views Hardware» more  DATE 2009»
15 years 5 months ago
Pipelined data parallel task mapping/scheduling technique for MPSoC
—In this paper, we propose a multi-task mapping/scheduling technique for heterogeneous and scalable MPSoC. To utilize the large number of cores embedded in MPSoC, the proposed te...
Hoeseok Yang, Soonhoi Ha
COCOON
2003
Springer
15 years 4 months ago
Petri Nets with Simple Circuits
We study the complexity of the reachability problem for a new subclass of Petri nets called simple-circuit Petri nets, which properly contains several well known subclasses such as...
Hsu-Chun Yen, Lien-Po Yu
ISCAS
2011
IEEE
261views Hardware» more  ISCAS 2011»
14 years 2 months ago
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level
— The last two decades have seen many efficient algorithms and architectures for the design of low-complexity bit-parallel Multiple Constant Multiplications (MCM) operation, tha...
Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Pa...
112
Voted
DAC
2003
ACM
16 years 3 days ago
Performance-impact limited area fill synthesis
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...
Yu Chen, Puneet Gupta, Andrew B. Kahng
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
15 years 11 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne