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ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
13 years 5 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
CONTEXT
2001
Springer
15 years 1 months ago
A Connectionist-Symbolic Approach to Modeling Agent Behavior: Neural Networks Grouped by Contexts
A recent report by the National Research Council (NRC) declares neural networks “hold the most promise for providing powerful learning models”. While some researchers have expe...
Amy E. Henninger, Avelino J. Gonzalez, Michael Geo...
74
Voted
ICS
2001
Tsinghua U.
15 years 1 months ago
Integrating superscalar processor components to implement register caching
A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a l...
Matt Postiff, David Greene, Steven E. Raasch, Trev...
GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
15 years 3 months ago
A table-based method for single-pass cache optimization
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank V...
96
Voted
ISCAPDCS
2007
14 years 11 months ago
Evaluation of architectural support for speech codecs application in large-scale parallel machines
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
Naeem Zafar Azeemi