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ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
15 years 3 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
RTSS
2006
IEEE
15 years 3 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
ICDCS
1999
IEEE
15 years 1 months ago
Design Considerations for Distributed Caching on the Internet
In this paper, we describe the design and implementation of an integrated architecture for cache systems that scale to hundreds or thousands of caches with thousands to millions o...
Renu Tewari, Michael Dahlin, Harrick M. Vin, Jonat...
RANDOM
2001
Springer
15 years 1 months ago
Minimizing Stall Time in Single and Parallel Disk Systems Using Multicommodity Network Flows
We study integrated prefetching and caching in single and parallel disk systems. A recent approach used linear programming to solve the problem. We show that integrated prefetching...
Susanne Albers, Carsten Witt
DATE
2004
IEEE
173views Hardware» more  DATE 2004»
15 years 1 months ago
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems
In embedded system-on-a-chip (SoC) applications, the need for integrating heterogeneous processors in a single chip is increasing. An important issue in integrating heterogeneous ...
Taeweon Suh, Douglas M. Blough, Hsien-Hsin S. Lee