16 search results - page 1 / 4 » An Integrated Approach for Synthesizing LUT Networks |
GLVLSI
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper presents a method for synthesizing lookup table (LUT) networks. The strategy employed by our method is very different from the strategies of previous methods; many deco...
FPL
2009
Springer
13 years 11 months ago
2009
Springer
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
FPGA
2012
ACM
12 years 1 months ago
2012
ACM
In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemente...
ICCAD
1993
IEEE
13 years 10 months ago
1993
IEEE
In this paper, we present an integrated approach to synthesis and mapping to go beyond the combinatorial limit set up by the depth-optimal FlowMap algorithm. The new algorithm, na...
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
In this paper a constructive library-aware multilevel logic synthesis approach using symmetries is described. It integrates the technology-independent and technologydependent stag...