631 search results - page 46 / 127 » An Integrated Formal Model of Scenarios Based on Statecharts |
105
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DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
The ForSyDe methodology has been developed for system level design. In this paper we present formal transformation methods for the refinement of an abstract and formal system mode...
103
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CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design...
EWSA
2005
Springer
15 years 3 months ago
2005
Springer
The growing importance of context-awareness in the construction of adaptable systems requires the development of formal models and notations that can bring this new dimension from ...
HICSS
2008
IEEE
15 years 4 months ago
2008
IEEE
Merging and integrating different conceptual models which have been developed by domain experts and analysts with dissimilar perspectives on the same issue has been the subject of...