30 search results - page 2 / 6 » An Integrated Partitioning and Scheduling Based Branch Decou... |
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
- This paper proposes a fast and practical decoupling capacitor (decap) budgeting algorithm to optimize the power ground (P/G) network design. The new method adopts a modified rand...
HPDC
2006
IEEE
14 years 12 days ago
2006
IEEE
This paper addresses the problem of efficient execution of a batch of data-intensive tasks with batch-shared I/O behavior, on coupled storage and compute clusters. Two scheduling...
ISSS
2000
IEEE
13 years 10 months ago
2000
IEEE
One important part of a HW/SW codesign system is the scheduler which is needed in order to determine if a given HW/SW partitioning is suitable for a given application. In this pap...
JUCS
2000
13 years 6 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
GLVLSI
2006
IEEE
14 years 12 days ago
2006
IEEE
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the c...