421 search results - page 14 / 85 » An Intelligent Parallel Loop Scheduling for Parallelizing Co... |
94
Voted
IPPS
2010
IEEE
14 years 7 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
IPPS
1998
IEEE
15 years 1 months ago
1998
IEEE
An effort to formalize the process of software pipelining loops with conditions is presented in this paper. A formal framework for scheduling such loops, based on representing set...
IEEEPACT
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper describes a compiler for stream programs that efficiently schedules computational kernels and stream memory operations, and allocates on-chip storage. Our compiler uses...
ICS
1995
Tsinghua U.
15 years 1 months ago
1995
Tsinghua U.
In this paper, we present a GSA-based technique that performs more e cient and more precise symbolic analysis of predicated assignments, recurrences and index arrays. The e ciency...
PPOPP
2010
ACM
15 years 6 months ago
2010
ACM
We present Lazy Binary Splitting (LBS), a user-level scheduler of nested parallelism for shared-memory multiprocessors that builds on existing Eager Binary Splitting work-stealing...