421 search results - page 21 / 85 » An Intelligent Parallel Loop Scheduling for Parallelizing Co... |
ICCAD
2001
IEEE
15 years 6 months ago
2001
IEEE
Tight data- and timing constraints are imposed by communication and multimedia applications. The architecture for the embedded processor imply resource constraints. Instead of ran...
HICSS
1996
IEEE
15 years 1 months ago
1996
IEEE
To take advantage of recent architectural improvements in microprocessors, advanced compiler optimizations such as software pipelining have been developed 1, 2, 3, 4]. Unfortunate...
IPPS
1999
IEEE
15 years 1 months ago
1999
IEEE
Parallelizing compiler technology has improved in recent years. One area in which compilers have made progress is in handling DOACROSS loops, where crossprocessor data dependencie...
ICPADS
2005
IEEE
15 years 3 months ago
2005
IEEE
Low energy consumptions are extremely important in real-time embedded systems, and scheduling is one of the techniques used to obtain lower energy consumptions. In this paper, we ...
TVLSI
2002
14 years 9 months ago
2002
Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the...