421 search results - page 43 / 85 » An Intelligent Parallel Loop Scheduling for Parallelizing Co... |
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
107
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ISCA
1992
IEEE
15 years 1 months ago
1992
IEEE
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...
58
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ICS
2005
Tsinghua U.
15 years 3 months ago
2005
Tsinghua U.
Chip Multiprocessors (CMPs) are flexible, high-frequency platforms on which to support Thread-Level Speculation (TLS). However, for TLS to deliver on its promise, CMPs must explo...
MICRO
2007
IEEE
15 years 3 months ago
2007
IEEE
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
HICSS
1995
IEEE
15 years 1 months ago
1995
IEEE
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...