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MICRO
1999
IEEE
110views Hardware» more  MICRO 1999»
15 years 1 months ago
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
Alexandre E. Eichenberger, Waleed Meleis
ICS
2005
Tsinghua U.
15 years 3 months ago
Low-power, low-complexity instruction issue using compiler assistance
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
Madhavi Gopal Valluri, Lizy Kurian John, Kathryn S...
ISSS
1995
IEEE
104views Hardware» more  ISSS 1995»
15 years 1 months ago
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis
One of the key issues in hardware/software{cosynthesis is precise estimation. The usual local estimation techniques are inadequate for globally optimising compilers and synthesis ...
Jörg Henkel, Rolf Ernst
CORR
2010
Springer
198views Education» more  CORR 2010»
14 years 9 months ago
Space and the Synchronic A-Ram
Space is a spatial programming language designed to exploit the massive parallelism available in a formal model of computation called the Synchronic A-Ram, and physically related ...
Alexander Victor Berka
APPT
2009
Springer
15 years 29 days ago
MaGate Simulator: A Simulation Environment for a Decentralized Grid Scheduler
Abstract. This paper presents a simulator for of a decentralized modular grid scheduler named MaGate. MaGate’s design emphasizes scheduler interoperability by providing intellige...
Ye Huang, Amos Brocco, Michèle Courant, B&e...