421 search results - page 58 / 85 » An Intelligent Parallel Loop Scheduling for Parallelizing Co... |
ESCIENCE
2007
IEEE
15 years 4 months ago
2007
IEEE
The emergence of computational grids has lead to an increased reliance on task schedulers that can guarantee the completion of tasks that are executed on unreliable systems. There...
ICASSP
2008
IEEE
15 years 4 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
TCAD
2002
14 years 9 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
ICPP
1993
IEEE
15 years 1 months ago
1993
IEEE
SIMD or vector computers and collection-oriented languages, like C , are designed to perform the same computation on each data item or on just a subset of the data. Subsets of pro...
HPCA
2001
IEEE
15 years 10 months ago
2001
IEEE
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high...