421 search results - page 64 / 85 » An Intelligent Parallel Loop Scheduling for Parallelizing Co... |
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
FPL
2009
Springer
15 years 2 months ago
2009
Springer
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
CASES
2007
ACM
15 years 1 months ago
2007
ACM
The key to increasing performance without a commensurate increase in power consumption in modern processors lies in increasing both parallelism and core specialization. Core speci...
106
click to vote
CEC
2005
IEEE
14 years 11 months ago
2005
IEEE
The problem of scheduling a parallel program given by a Directed Acyclic Graph (DAG) of tasks is a well-studied area. We present a new approach which employs Differential Evolution...
HPCC
2009
Springer
15 years 2 months ago
2009
Springer
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...