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IPPS
2009
IEEE
15 years 4 months ago
Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
IEEEPACT
2000
IEEE
15 years 2 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier
CC
2009
Springer
149views System Software» more  CC 2009»
15 years 10 months ago
Exploiting Speculative TLP in Recursive Programs by Dynamic Thread Prediction
Speculative parallelisation represents a promising solution to speed up sequential programs that are hard to parallelise otherwise. Prior research has focused mainly on parallelisi...
Lin Gao 0002, Lian Li 0002, Jingling Xue, Tin-Fook...
CP
2004
Springer
15 years 3 months ago
A Hybrid Method for Planning and Scheduling
We combine mixed integer linear programming (MILP) and constraint programming (CP) to solve planning and scheduling problems. Tasks are allocated to facilities using MILP and sche...
John N. Hooker
IJHR
2008
117views more  IJHR 2008»
14 years 9 months ago
Implementation of Cognitive Control for a Humanoid Robot
Engineers have long used control systems utilizing models and feedback loops to control realworld systems. Limitations of model-based control led to a generation of intelligent co...
Kazuhiko Kawamura, Stephen M. Gordon, Palis Ratana...