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» An Interconnect Energy Model Considering Coupling Effects
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ICCAD
2005
IEEE
132views Hardware» more  ICCAD 2005»
15 years 6 months ago
Serial-link bus: a low-power on-chip bus architecture
As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. ...
Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khell...
76
Voted
TCAD
2008
89views more  TCAD 2008»
14 years 9 months ago
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning
We present in this paper a new interconnect-driven multilevel floorplanner, called interconnect-driven multilevelfloorplanning framework (IMF), to handle large-scale buildingmodule...
Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin
81
Voted
RTSS
2006
IEEE
15 years 3 months ago
System-Level Energy Management for Periodic Real-Time Tasks
In this paper, we consider the system-wide energy management problem for a set of periodic real-time tasks running on a DVS-enabled processor. Our solution uses a generalized powe...
Hakan Aydin, Vinay Devadas, Dakai Zhu
90
Voted
ISLPED
2007
ACM
138views Hardware» more  ISLPED 2007»
14 years 11 months ago
Power optimal MTCMOS repeater insertion for global buses
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
Hanif Fatemi, Behnam Amelifard, Massoud Pedram
79
Voted
DAC
1998
ACM
15 years 10 months ago
Figures of Merit to Characterize the Importance of On-Chip Inductance
- A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicromete...
Yehea I. Ismail, Eby G. Friedman, José Luis...