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» An Interconnect Energy Model Considering Coupling Effects
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63
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VLSI
2010
Springer
14 years 8 months ago
Fine-grained post placement voltage assignment considering level shifter overhead
—Multi-Vdd techniques enable application of lower supply voltage levels on cells with timing slacks. New voltage assignment, placement and voltage island partitioning methods are...
Zohreh Karimi, Majid Sarrafzadeh
HPCA
2005
IEEE
15 years 3 months ago
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses
With technology scaling, power dissipation and localized heating in global and semi-global bus wires are becoming increasingly important, and this necessitates the development of ...
Krishnan Sundaresan, Nihar R. Mahapatra
79
Voted
PAMI
1998
141views more  PAMI 1998»
14 years 9 months ago
A Probabilistic Approach to the Coupled Reconstruction and Restoration of Underwater Acoustic Images
—This paper describes a probabilistic technique for the coupled reconstruction and restoration of underwater acoustic images. The technique is founded on the physics of the image...
Vittorio Murino, Andrea Trucco, Carlo S. Regazzoni
DATE
2003
IEEE
101views Hardware» more  DATE 2003»
15 years 3 months ago
On Modeling Cross-Talk Faults
Circuit marginality failures in high performance VLSI circuits are projected to increase due to shrinking process geometries and high frequency design techniques. Capacitive cross...
Sujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, ...
DAC
1995
ACM
15 years 1 months ago
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pil...