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» An Introduction to Low-Density Parity-Check Codes
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ICC
2007
IEEE
192views Communications» more  ICC 2007»
14 years 17 days ago
Informed Dynamic Scheduling for Belief-Propagation Decoding of LDPC Codes
— Low-Density Parity-Check (LDPC) codes are usually decoded by running an iterative belief-propagation, or message-passing, algorithm over the factor graph of the code. The tradi...
Andres I. Vila Casado, Miguel Griot, Richard D. We...
DFT
2007
IEEE
135views VLSI» more  DFT 2007»
14 years 18 days ago
Fault Secure Encoder and Decoder for Memory Applications
We introduce a reliable memory system that can tolerate multiple transient errors in the memory words as well as transient errors in the encoder and decoder (corrector) circuitry....
Helia Naeimi, André DeHon
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 8 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
AP2PS
2009
IEEE
13 years 9 months ago
Algorithm-Based Fault Tolerance Applied to P2P Computing Networks
—P2P computing platforms are subject to a wide range of attacks. In this paper, we propose a generalisation of the previous disk-less checkpointing approach for fault-tolerance i...
Thomas Roche, Mathieu Cunche, Jean-Louis Roch
ISCAS
2005
IEEE
170views Hardware» more  ISCAS 2005»
13 years 12 months ago
Quantized LDPC decoder design for binary symmetric channels
Abstract— Binary Symmetric Channels (BSC) like the Interchip buses and the Intra-chip buses are gaining a lot of attention due to their widespread use with multimedia storage dev...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra