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ICCAD
1994
IEEE
111views Hardware» more  ICCAD 1994»
15 years 3 months ago
On modeling top-down VLSI design
We present an improved data model that reflects the whole VLSI design process including bottom-up and topdown design phases. The kernel of the model is a static version concept th...
Bernd Schürmann, Joachim Altmeyer, Martin Sch...
ICCAD
2009
IEEE
89views Hardware» more  ICCAD 2009»
14 years 9 months ago
Decoupling capacitance efficient placement for reducing transient power supply noise
Decoupling capacitance (decap) is an efficient way to reduce transient noise in on-chip power supply networks. However, excessive decap may cause more leakage power, chip resource...
Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. T...
FDL
2005
IEEE
15 years 5 months ago
Integrating Model-Checking with UML-based SoC Development
In order to address the complexities of SoC design, rigorous development methods and automated tools are required. This paper presents an approach to formal verification using mod...
Peter Green, Kinika Tasie-Amadi
ANOR
2006
133views more  ANOR 2006»
14 years 12 months ago
An integrated model for logistics network design
In this paper we introduce a new formulation of the logistics network design problem encountered in deterministic, single-country, single-period contexts. Our formulation is flexi...
Jean-François Cordeau, Federico Pasin, Mari...
TCAD
2010
136views more  TCAD 2010»
14 years 6 months ago
Bounded Model Debugging
Design debugging is a major bottleneck in modern VLSI design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical des...
Brian Keng, Sean Safarpour, Andreas G. Veneris