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» An O(nlogn) time algorithm for optimal buffer insertion
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FCCM
2005
IEEE
106views VLSI» more  FCCM 2005»
15 years 3 months ago
High-Performance FPGA-Based General Reduction Methods
FPGA-based floating-point kernels must exploit algorithmic parallelism and use deeply pipelined cores to gain a performance advantage over general-purpose processors. Inability t...
Gerald R. Morris, Ling Zhuo, Viktor K. Prasanna
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
15 years 3 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
COMCOM
2010
131views more  COMCOM 2010»
14 years 8 months ago
Level the buffer wall: Fair channel assignment in wireless sensor networks
—In this paper, we study the trade-off between network throughput and fairness in a multi-channel enabled WSN. Traditional approaches attempt to solve the two problems in an isol...
Yanyan Yang, Yunhuai Liu, Lionel M. Ni
IPL
2008
97views more  IPL 2008»
14 years 9 months ago
Dynamic polar diagram
The Polar Diagram [1] of a set of points (i.e. sites) is a partition of the plane. It is a locus approach for problems processing angles. Also, Dynamic Polar Diagram problem is a ...
Bahram Sadeghi Bigham, Ali Mohades, Lidia M. Orteg...
GRID
2004
Springer
15 years 2 months ago
Design and Analysis of a Dynamic Scheduling Strategy with Resource Estimation for Large-Scale Grid Systems
In this paper, we present a resource conscious dynamic scheduling strategy for handling large volume computationally intensive loads in a Grid system involving multiple sources an...
Sivakumar Viswanathan, Bharadwaj Veeravalli, Danto...